1. Field of Invention
The present invention relates to a bump structure and a manufacturing method thereof, and more particularly, to a stacked bump structure and a manufacturing method thereof.
2. Description of the Related Art
In the semiconductor industry, the fabrication of integrated circuits (ICs) may be roughly divided into three stages: IC design, IC process and IC packaging.
During the IC process, a chip is fabricated by making a wafer, forming ICs and dicing the wafer. Generally speaking, the wafer has an active surface, generally referred to the surface having active devices. After the fabrication of the ICs within the wafer, multiple bonding pads are formed on the active surface of the wafer, so that a chip formed by dicing the wafer is able to be electrically connected to a carrier via the bonding pads. The carrier may be, for example, a leadframe or a package substrate. The chip may be connected to the carrier through wire bonding or flip chip technology, so as to form the electrical connection between the bonding pads of the chip and the pads of the carrier for forming a chip package.
For the wire bonding technology, except for the above-mentioned method that the bonding pads of the chip are electrically connected to the pads of the carrier, two bonding pads of the chip may be electrically connected to each other through a bonding wire according to the design requirement, which is the so-called stand-off stitch bonding (SSB).
FIG. 1 is a schematic diagram showing a conventional chip using the stand-off stitch bonding. Referring to FIG. 1, a conventional chip 100 has multiple bonding pads 110 disposed on a surface 120 of the chip 100. From FIG. 1, two adjacent bonding pads 110 of the chip 100 are electrically connected to each other by using SSB. However, if the pad pitch d1 between two adjacent pads 110 is too close, the space limitation makes the bonding wire W1 curve drastically, which leads to the defect of the wire, so as to degrade the electrical performance initially designed for electrically connecting the two adjacent pads 110, even to break the circuit. Thus, the yield rate of the chip 100 is reduced.